View LC72348G_258928.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Ordering number : ENN6472
CMOS IC
LC72348G/W, 72349G/W
Low-Voltage ETR Controller with On-Chip LCD Driver
Overview
The LC72348G/W and LC72349G/W are low-voltage electronic tuning microcontrollers that include a PLL that operates up to 230 MHz and a 1/4 duty 1/2 bias LCD driver on chip. These ICs can contribute to further end product cost reduction than the LC72341 series while providing improved standby current characteristics. Also these ICs can use the application program for the LC72341 series except the IF counter function. These ICs are optimal for use in low-voltage portable audio equipment that includes a radio receiver.
Package Dimensions
unit: mm 3231-QIP64G
[LC72348G, 72349G]
17.2 14.0 0.8 0.35 1.6 1.0 0.15
1.0
48
1.6 1.0
33 32
49
Function
* Program memory (ROM): -- 3072 x 16 bits (6K bytes) LC72348G/W -- 4096 x 16 bits (8K bytes) LC72349 G/W * Data memory (RAM): -- 192 x 4 bits LC72348 G/W -- 256 x 4 bits LC72349 G/W * Cycle time: 40 s (all 1-word instructions) at 75kHz crystal oscillation * Stack: 8 levels * LCD driver: 48 to 80 segments (1/4 duty, 1/2 bias drive) * Interrupts: One external interrupt Timer interrupts (1, 5, 10, and 50 ms) * A/D converter: Three input channels (5-bit successive approximation conversion) * Input ports: 7 ports (of which three can be switched for use as A/D converter inputs) * Output ports: 6 ports (of which 1 can be switched for use as the beep tone output and 2 are opendrain ports) * I/O ports: 16 ports (of which 8 can be switched for use as LCD ports and as mask options)
Continued on next page.
17.2 14.0 0.8
17
3.0max
64
1.0
1
16
0.1 2.15
15.6
0.8
SANYO: QFP64G
unit: mm 3190-SQFP64
[LC72348W, 72349W]
12.0 10.0 1.25
48 49
0.5
0.18
1.25
33 32
0.15
12.0 10.0 0.5
1.25
64
17 1 16
0.5
0.1 0.5
1.7max
1.25
SANYO: SQFP64
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
32700RM (OT) No. 6472-1/14
LC72348G/W, 72349G/W
Continued from preceding page.
* PLL: Supports dead zone control (two types) * Reference frequencies: 1, 3, 3.125, 5, 6.25, 12.5, and 25 kHz * Input frequencies: FM band: 10 to 230 MHz AM band: 0.5 to 10 MHz * Input sensitivity: FM band: 35 mVrms (50 mVrms at 130 MHz or higher frequency) AM band: 35 mVrms * External reset input: During CPU and PLL operations, instruction execution is started from location 0. * Built-in power-on reset circuit: The CPU starts execution from location 0 when power is first applied. * Halt mode: The controller-operating clock is stopped.
* Backup mode: The crystal oscillator is stopped. * Static power-on function: Backup state is cleared with the PF port * Beep tone: 1.5 and 3.1 kHz * Built-in tuner voltage generating circuit: Cost reduced in tuner-use power supply circuit * Built-in low-pass filter amplifier * Optional function switches: -- PH0 to PH3 (general-purpose input, open-drain output/general-purpose input and output/S13 to S16) -- PG0 to PG3 (general-purpose input, open-drain output/general-purpose input and output/S17 to S20) -- VSENSE circuit (provided/not provided) -- FM DC/DC clock (1/256, 75 kHz) * Memory retention voltage: 0.9 V at least * Package: SQFP-64 (0.5-mm pitch), QIC-64 (0.8-mm pitch)
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Input voltage Output voltage Symbol VDD max VIN VOUT(1) VOUT(2) IOUT(1) IOUT(2) Output current IOUT(3) IOUT(4) IOUT(5) Allowable power dissipation Operating temperature Storage temperature Pdmax Topr Tstg All input pins AOUT, PE All output pins except VOUT(1) PC, PD, PG, PH, EO PB AOUT, PE S1 to S20 COM1 to COM4 Ta = -20 to +70C Conditions Ratings -0.3 to +4.0 -0.3 to VDD +0.3 -0.3 to +15 -0.3 to VDD + 0.3 0 to 3 0 to 1 0 to 2 300 3 300 -20 to +70 -45 to +125 Unit V V V V mA mA mA A mA mW C C
No. 6472-2/14
LC72348G/W, 72349G/W Allowable Operating Ranges at Ta = -20 to +70C, VDD = 1.8 to 3.6 V
Parameter Symbol VDD(1) Supply voltage VDD(2) VDD(3) VDD(4) VIH(1) Input high-level voltage VIH(2) VIH(3) VIL(1) Input low-level voltage VIL(2) VIL(3) VIN(1) Input amplitude VIN(2) VIN(3) Input voltage range VIN(5) FIN(1) Input frequency FIN(2) FIN(3) FIN(4) Conditions PLL operating voltage Memory retention voltage CPU operating voltage A/D converter operating voltage Input ports other than VIH(2), VIH(3), AMIN, FMIN, and XIN RES Port PF Input ports other than VIL(2), VIL(3), AMIN, FMIN, and XIN RES Port PF XIN FMIN, AMIN FMIN ADIO, ADI1, ADI3 XIN: CI 35 k FMIN: VIN(2), VDD(1) FMIN: VIN(3), VDD(1) AMIN(L): VIN(2), VDD(1) Ratings min 1.8 1.0 1.4 1.6 0.7 VDD 0.8 VDD 0.6 VDD 0 0 0 0.5 0.035 0.05 0 70 10 130 0.5 75 3.0 3.0 3.6 3.6 VDD VDD VDD 0.3 VDD 0.2 VDD 0.2 VDD 0.6 0.35 0.35 VDD 80 130 250 10 V V V V V V Vrms Vrms Vrms V kHz MHz MHz MHz typ 3.0 max 3.6 V Unit
Electrical Characteristics within the allowable operating ranges
Parameter Symbol IIH(1) IIH(2) Input high-level current IIH(3) IIL(1) IIL(2) Input low-level current IIL(3) Input floating voltage Pull-down resistor values Hysteresis Voltage doubler reference voltage Voltage doubler step-up voltage VIF RPD(1) RPD(2) VH DBR4 DBR1, 2, 3 VOH(1) VOH(2) Output high-level voltage VOH(3) VOH(4) VOH(5) VOH(6) Conditions XIN: VI = VDD = 3.0 V FMIN, AMIN: VI = VDD = 3.0 V PA/PF (without pull-down resistors), the PC, PD, PG, and PH ports, and RES: VI = VDD = 3.0 V XIN: VI = VDD = VSS FMIN, AMIN: VI = VDD = VSS PA/PF (without pull-down resistors), the PC, PD, PG, and PH ports, and RES: VI = VDD = VSS PA/PF (with pull-down resistors) PA/PF (with pull-down resistors), VDD = 3.0 V TEST1, TEST2 RES Referenced to VDD, C(3) = 0.47 F, Ta = 25C *1 C(1) = 0.47 F C(2) = 0.47 F, without loading, Ta = 25C *1 PB: IO = -1 mA PC, PD, PG, PH: IO = -1 mA EO: IO = -500 A XOUT: IO = -1 A S1 to S20: IO = -20 A *1 COM1, COM2, COM3, COM4: IO = -100 A *1 0.1 VDD 1.3 2.7 VDD - 0.7 VDD VDD - 0.3 VDD VDD - 0.3 VDD VDD - 0.3 VDD 2.0 2.0 75 100 10 0.2 VDD 1.5 3.0 1.7 3.3 VDD - 0.3 VDD -3 -8 3 8 Ratings min typ max 3 20 3 -3 -20 -3 0.05 VDD 200 Unit A A A A A A V k k V V V V
V V V V V
Continued on next page.
No. 6472-3/14
LC72348G/W, 72349G/W
Continued from preceding page.
Parameter Symbol VOL(1) VOL(2) VOL(3) VOL(4) Output low-level voltage VOL(5) VOL(6) VOL(7) VOL(8) Output off leakage current A/D converter error Supply voltage drop detection voltage Supply voltage rise detection voltage VSENSE(1) VSENSE(2) IDD(1) IDD(2) Current drain IDD(3) IDD(4) IOFF(1) IOFF(2) PB: IO = -50 A PC, PD, PE, PG, PH: IO = -1 mA EO: IO = -500 A XOUT: IO = -1 A S1 to S20: IO = -20 A *1 COM1, COM2, COM3, COM4: IO = -100 A *1 PE: IO = 2 mA AOUT(AIN = 1.3 V), TU: IO = 1 mA, VDD = 3 V Ports PB, PC, PD, PG, PH, and EO AOUT and port PE ADI0, ADI1, ADI3 VDD(4) Ta = 25C *2 Ta = 25C *2 VDD(1): FIN(2) 130 MHz, Ta = 25C VDD(2): In HALT mode, Ta = 25C *3 VDD = 3.6 V, with the oscillator stopped, Ta = 25C *4 VDD = 1.8 V, with the oscillator stopped, Ta = 25C *4 -3 -100 -1/2 1.6 (1)min +0.1 5 0.1 1 0.5 1.75 Conditions Ratings min 0.3 VDD typ max 0.7 VDD 0.3 VDD 0.3 VDD 0.3 VDD 1.0 1.0 1.0 0.5 +3 +100 +1/2 1.9 (1)max +0.2 15 Unit V V V V V V V V A nA LSB V V mA mA A A
Note: The halt mode current is due to the CPU executing 20 instruction steps every 125 ms.
Pin Assignment
XIN TEST1 AGND AOUT AIN EO VSS AMIN FMIN VDD TU RES DBR1 DBR2 DBR3 DBR4 XOUT TEST2 PA3 PA2 PA1 PA0 PB3 PB2 PB1 PB0 PC3 PC2 PC1 PC0 PD3 PD2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
1 2 3 4 5 6 7 8 9
LC72348G, 72348W LC72349G, 72349W
10 11 12 13 14 15
16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
COM1 COM2 COM3 COM4 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12
PD1 INT/PD0 PE1 BEEP/PE0 ADI3/PF2 ADI1/PF1 ADI0/PF0 VSS PG3/S20 PG2/S19 PG1/S18 PG0/S17 PH3/S16 PH2/S15 PH1/S14 PH0/S13
No. 6472-4/14
LC72348G/W, 72349G/W Note: * C(1), C(2), and C(3) must be connected even if an LCD is not used.
0.1 to 1 F C(C1) 0.1 to 1 F 0.1 to 1 F C(C3) C(C2)
DBR1 DBR2 DBR3 DBR4
Notes: *1. The capacitors C(1), C(2), and C(3) must be connected to the DBR pins. *2. VSENSE When the VDD voltage drops, the VSENSE flag is set when that voltage is 1.75 V (typical). Applications can check the VSENSE flag using the TST instruction. Battery or other power source depletion can be easily measured by monitoring this flag. Note that the voltage for VSENSE detection differs for the falling and rising directions. Thus, after the VSENSE flag has been set due to a voltage drop, it will not be reset if the voltage rises by under 0.1 V.
VDD VDD 2.1 V 1.9 V 1.6 V RESET 1.7 V SET t SET RESET t
VSENSE (1) For a falling voltage
VSENSE (2) For a rising voltage
*3. Halt mode current measurement circuit
*4. Backup mode current measurement circuit
7 pF 75 kHz
A
7 pF 75 kHz 0.1 F 0.1 F 0.1 F FMIN AMIN TEST1, 2 7pF
A
7pF
XOUT VDD RES DBR1 XIN DBR2 DBR3 FMIN AMIN TEST1, 2 DBR4 VSS PA, PF AGND AIN
XOUT VDD RESDBR1 XIN DBR2 DBR3 DBR4 VSS AGND AIN
0.1 F 0.1 F 0.1 F
With all ports other than those specified above left open. With output mode selected for PC and PD. With segments S13 to S20 selected.
With all ports other than those specified above left open. With output mode selected for PC and PD. With segments S13 to S20 selected.
No. 6472-5/14
LC72348G/W, 72349G/W Block Diagram
XIN XOUT FMIN AMIN
DIVIDER SYSTEM CLOCK GENERATOR 1/2 1/16,1/17
REFERENCE DIVIDER
PHASE DETECTOR 75kHz
EO
PROGRAMMBLE DIVIDER 1/2
FM LOCAL 1/256 AM LOCAL 1/2
TU
PLL DATA LATCH VDD VSS VSENSE TIME BASE COUNT CONTROL END
PLL CONTROL
LCDA/B
S1
SEG 4 LA 7 LCPA/B
LCD 80 PORT DRIVER
RES
*
P-ON RESET TEST1 TEST2 PA0 PA1 PA2 PA3 PB0 PB1 PB2 PB3 PC0 PC1 PC2 PC3 INT/PD0 PD1 PD2 PD3 AIN AOUT AGND
*
S12 RAM ADDRESS 192 x 4bits(LC72348) DECODER 256 x 4bits(LC72349) BANK S13/PH0 S14/PH1 S15/PH2 S16/PH3 S17/PG0 S18/PG1 S19/PG2 S20/PG3 DBR1 DBR2 DBR3 DBR4 COM4 COM3 COM2 COM1
BUS DRIVER ROM DATA LATCH / BUS DRIVER DATA LATCH / BUS DRIVER DATA LATCH / BUS DRIVER 3k x 16bits (LC72348) 4k x 16bits (LC72349) ADDRESS DECODER BUS CONTROL
DATA LATCH / BUS DRIVER DATA LATCH / BUS DRIVER DOUBLER CIRCUIT
INSTRUCTION DECODER SKIP
JMP 14 CAL ADDRESS COUNTER RETURN INTERRUPT 14 RESET STACK BANK CF
COMMON DRIVER
BEEP TONE DATA LATCH BUS DRIVER
/
PE0/BEEP MPX PE1
LATCH A ALU LATCH B TIMER 0
JUDGE
MPX ADC (5bits)
DATA LATCH BUS DRIVER
/
PF0/ADI0 PF1/ADI1 PF2/ADI3
DATA BUS
No. 6472-6/14
LC72348G/W, 72349G/W Pin Functions
Pin No. Pin I/O Function I/O circuit
64 1
XIN XOUT
I O
75 kHz oscillator connections
63 2
TEST1 TEST2
I I
IC testing. These pins must be connected to ground during normal operation.
--
Input with built-in pull-down resistor 6 5 4 3 PA0 PA1 PA2 PA3 I Special-purpose key return signal input ports designed with a low threshold voltage. When used in conjunction with port PB to form a key matrix, up to 3 simultaneous key presses can be detected. The four pull-down resistors are selected together in a single operation using the IOS instruction (PWn = 2, b1); they cannot be specified individually. Input is disabled in backup mode, and the pull-down resistors are disabled after a reset.
General-purpose CMOS and n-channel open-drain output shared-function ports. The IOS instruction (Pwn = 2) is used for function switching. 10 9 8 7 PB0 PB1 PB2 PB3 O (b0: PB0, b2: PB1, b3: PB2, PB3) (0: general-purpose CMOS, 1: n-channel opendrain) Special-purpose key source signal output ports. Since unbalanced CMOS output transistor circuits are used, diodes to prevent short-circuits when multiple keys are pressed are not required. These ports go to the output high-impedance state in backup mode. These ports go to the output high-impedance state after a reset and remain in that state until an output instruction (OUT, SPB, or RPB) is executed. *: Verify the output impedance conditions carefully if these pins are used for functions other than key source outputs. 14 13 12 11 PC0 PC1 PC2 PC3 I/O 18 17 16 15 INT/PD0 PD1 PD2 PD3 *2 General-purpose output ports with shared beep tone output function (PE0 only). The BEEP instruction is used to switch PE0 between the general-purpose output port and beep tone output functions. To use PE0 as a general-purpose output port, execute a BEEP instruction with b2 set to 0. Set b2 to 1 to use PE0 as the beep tone output port. The b0 and b1 bits are used to select the beep tone frequency. There are two beep tone frequencies supported. 20 19 BEEP/PE0 PE1 *: When PE0 is set up as the beep tone output, executing an output instruction to PE0 only changes the state of the internal output latch, it does not affect the beep tone output in any way. Only the PE0 pin can be switched between the general-purpose output function and the beep tone output function; the PE1 pin only functions as a general-purpose output. These pins go to the high-impedance state in backup mode and remain in that state until an output instruction or a BEEP instruction is executed. Since these ports are open-drain ports, resistors must be inserted between these pins and VDD. These ports are set to general-purpose output port function after a reset. General-purpose I/O ports. PD0 can be used as an external interrupt port. Input or output mode can be set individually using the IOS instruction by the bit (Pwn = 4, 5). A value of 0 specifies input, and 1 specifies output. These ports go to the input disabled high-impedance state in backup mode. They are set to function as general-purpose input ports after a reset.
Unbalanced CMOS pushpull/n-channel open-drain
CMOS push-pull
N-channel open-drain
Continued on next page.
No. 6472-7/14
LC72348G/W, 72349G/W
Continued from preceding page.
Pin No. Pin I/O Function General-purpose input and A/D converter input shared function ports. The IOS instruction (Pwn = FH) is used to switch between the general-purpose input and A/D converter port functions. The general-purpose input and A/D converter port functions can be switched by the bit, with 0 specifying general-purpose input, and 1 specifying the A/D converter input function. To select the A/D converter function, set up the A/D converter pin with an IOS instruction with Pwn set to 1. The A/D converter is started with the UCC instruction (b3 = 1, b2 = 1). The ADCE flag is set when the conversion completes. The INR instruction is used to read in the data. *: If an input instruction is executed for one of these pins which is set up for analog input, the read in data will be at the low level since CMOS input is disabled. In backup mode these pins go to the input disabled high-impedance state. These ports are set to their general-purpose input port function after a reset. The A/D converter is a 5-bit successive approximation type converter, and features a conversion time of 1.28 ms. Note that the full-scale A/D converter voltage (1FH) is (63.96) VDD. LCD driver segment output, general-purpose I/O, and general-purpose n-channel open-drain output shared function ports. The IOS instruction is used for switching between the segment output and generalpurpose I/O functions. 25 26 27 28 PG3/S20 PG2/S19 PG1/S18 PG0/S17 I/O 29 30 31 32 PH3/S16 PH2/S15 PH1/S14 PH0/S13 *2 * When used as segment output ports The general-purpose I/O port function is selected with the IOS instruction (Pwn = 8). b0 = S17 to 20/PG0 to 3 (0: Segment output, 1: PG0 to 3) The general-purpose I/O port function is selected with the IOS instruction (Pwn = 9). b0 = S13 to 16/PH0 to 3 (0: Segment output, 1: PH0 to 3) * When used as general-purpose I/O ports The IOS instruction (Pwn = 6,7) is used to select input or output. Note that the mode can be set in individual by the bit. b0 = PG0 b1 = PG1 b2 = PG2 b3 = PG3 0: Input 1: Output b0 = PH0 b1 = PH1 b2 = PH2 b3 = PH3 0: Input 1: Output CMOS push-pull I/O circuit CMOS input/analog input
23 22 21
PF0/ADI0 PF1/ADI1 PF2/ADI3 I
In backup mode, these pins go to the input disabled high-impedance state if set up as general-purpose outputs, and are fixed at the low level if set up as segment outputs. These ports are set up as segment outputs after a reset. Although the general-purpose I/O port/general-purpose n-channel open-drain output/LCD port setting is a mask option, the IOS instruction must be used as described above to set up the port function. CMOS push-pull LCD driver segment output pins.
33 to 44
A 1/4-duty 1/2-bias drive technique is used. S16 to S1 O The frame frequency is 75 Hz. In backup mode, the outputs are fixed at the low level. After a reset, the outputs are fixed at the low level.
45 46 47 48
COM4 COM3 COM2 COM1 O
LCD driver common output pins. A 1/4-duty 1/2-bias drive technique is used. The frame frequency is 75 Hz. In backup mode, the outputs are fixed at the low level. After a reset, the outputs are fixed at the low level.
49 50 51 52
DBR4 DBR3 DBR2 DBR1 I LCD power supply step-up voltage inputs.
Continued on next page.
No. 6472-8/14
LC72348G/W, 72349G/W
Continued from preceding page.
Pin No. Pin I/O System reset input. 53 RES I In CPU operating mode or halt mode, applications must apply a low level for at least one full machine cycle to reset the system and restart execution with the PC set to location 0. This pin is connected in parallel with the internal power on reset circuit. Tuning voltage generation circuit outputs. These pins include an n-channel transistor, and a tuning voltage can be generated by connecting external coil, diode, and capacitor components. FM DC-DC clock switching is a mask option. 54 TU O DC-DC clock AM FM AM local 1/2 FM local 1/256 or 75 kHz CMOS amplifier input FM VCO (local oscillator) input. 56 FMIN I This pin is selected with the PLL instruction CW1. The input must be capacitor coupled. Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode. N-channel open-drain Function I/O circuit
AM VCO (local oscillator) input. This pin and the bandwidth are selected with the PLL instruction CW1. CW1 b1, b0 1 1 Bandwidth 0.5 to 10 MHz (MW, LW)
CMOS amplifier input
57
AMIN
I
The input must be capacitor coupled. Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode. CMOS push-pull Main charge pump output. When the local oscillator frequency divided by N is higher than the reference frequency a high level is output, when lower, a low level is output. The pin is set to the high-impedance state when the frequencies match. Output goes to the high-impedance state in backup mode, in halt mode, after a reset, and in PLL stop mode.
59
EO
O
60 61 62
AIN AOUT AGND O
Transistor used for the low-pass filter amplifier. Connect AGND to ground.
24 58 55 Note 2:
VSS VSS VDD --
Power supply pin.
This pin must be connected to ground. This pin must be connected to ground. This pin must be connected to VDD. --
When a pin in an I/O switching port is used as an output, applications must first set up the data with an OUT, SPB, or RPB instruction and then set up output mode with an IOS instruction.
No. 6472-9/14
LC72348G/W, 72349G/W Sample Application for Tuning Voltage Generation Circuit Sample Application for Low-Pass Filter Amplifier
XIN
64
XOUT
1
75kHz
EO
59
VDD
55
AIN
Mask option
60
FMIN
56
1/256 AMIN
FM mode
AOUT
Varactor
61
AGND 1/2
AM mode
57
TU+B
62
TU
54
RADIO ON
LC72348 DC-DC converter load: 100 k
12
FM reception mode clock (75 kHz selected) AM reception mode clock frequency range
10
8
VT voltage --V
6
4
2
0 10 100
Clock frequency -- kHz
1000
10000
No. 6472-10/14
LC72348G/W, 72349G/W LC72340 Series Instruction Set Terminology ADDR b C DH DL I M N Rn Pn PW r ( ), [ ] M (DH, DL) : Program memory address : Borrow : Carry : Data memory address High (Row address) [2 bits] : Data memory address Low (Column address) [4 bits] : Immediate data [4 bits] : Data memory address : Bit position [4 bits] : Resister number [4 bits] : Port number [4 bits] : Port control word number [4 bits] : General register (One of the addresses from 00H to 0FH of BANK0) : Contents of register or memory : Data memory specified by DH, DL
Instructions
Mnemonic AD ADS
Operand 1st r r r r M M M M r r r r M M M M 2nd M M M M I I I I M M M M I I I I Add M to r
Function
Operations function r (r) + (M) r (r) + (M), skip if carry r (r) + (M) + C r (r) + (M) + C skip if carry M (M) + I M (M) + I, skip if carry M (M) + I + C M (M) + I + C, skip if carry r (r) - (M) r (r) - (M), skip if borrow r (r) - (M) - b r (r) - (M) - b, skip if borrow M (M) - I M (M) - I, skip if borrow M (M) - I - b M (M) - I - b, skip if borrow
Instruction format f 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 e 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 d 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 c 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 a 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 9 8 7 6 5 4 3 2 r r r r I I I I r r r r I I I I 1 0
DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH
DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL
Add M to r, then skip if carry Add M to r with carry Add M to r with carry, then skip if carry Add I to M Add I to M, then skip if carry Add I to M with carry Add I to M with carry, then skip if carry Subtract M from r Subtract M from r, then skip if borrow Subtract M from r with borrow Subtract M from r with borrow, then skip if borrow Subtract I from M Subtract I from M, then skip if borrow Subtract I from M with borrow Subtract I from M with borrow, then skip if borrow
Addition instructions
AC ACS AI AIS AIC AICS SU SUS
Subtraction instructions
SB SBS SI SIS SIB SIBS
Continued on next page.
No. 6472-11/14
LC72348G/W, 72349G/W
Continued from preceding page.
Instructions
Mnemonic SEQ SEQI SNEI SGE SGEI SLEI AND
Operand 1st r M M r M M r M r M r M r r M r M M1 M M M M r M r M2 I N N 2nd M I I M I I M I M I M I
Function Skip if r equal to M Skip if M equal to I Skip if M not equal to I Skip if r is greater than or equal to M Skip if M is greater than equal to I Skip if M is less than I AND M with r AND I with M OR M with r OR I with M Exclusive OR M with r Exclusive OR M with M Shift r right with carry Load M to r Store r to M Move M to destination M referring to r in the same row Move source M referring to r to M in the same row Move M to M in the same row Move I to M Test M bits, then skip if all bits specified are true Test M bits, then skip if all bits specified are false Jump to the address Call subroutine Return from subroutine Return from interrupt
Operations function (r) - (M), skip if zero (M) - I, skip if zero (M) - I, skip if not zero (r) - (M), skip if not borrow (M) - I, skip if not borrow (M) - I, skip if borrow r (r) AND (M) M (M) AND I r (r) OR (M) M (M) OR I r (r) XOR (M) M (M) XOR I carry (r) r (M) M (r) [DH, Rn] (M) M [DH, Rn] [DH, DL1] [DH, DL2] MI
Instruction format f 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 e 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 d 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 c 1 1 0 1 1 0 0 0 0 0 1 1 0 1 1 1 1 0 0 1 1 b 0 0 0 1 1 1 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 a 0 1 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 9 8 7 6 5 4 3 2 r I I r I I r I r I r I 0 r r r r r DL2 I N N 1 0
Comparison instructions
DH DH DH DH DH DH DH DH DH DH DH DH 0 0 1
DL DL DL DL DL DL DL DL DL DL DL DL 1 1
Logic instructions
ANDI OR ORI EXL EXLI SHR LD
DH DH DH DH DH DH DH DH
DL DL DL DL DL1 DL DL DL
Transfer instructions
ST MVRD MVRS MVSR MVI
Jump and subroutine Bit test call instructions instructions
TMT TMF JMP CAL RT RTI
if M (N) = all 1s, then skip 1 if M (N) = all 0s, then skip 1 PC ADDR PC ADDR Stack (PC) + 1 PC Stack PC Stack, BANK Stack, CARRY Stack 1 1 0 0
ADDR ADDR
ADDR (13 bits) ADDR (13 bits) 0 0 1 1 0 0 0 0 0 1
Continued on next page.
No. 6472-12/14
LC72348G/W, 72349G/W
Continued from preceding page.
Instructions
Mnemonic SS
Operand 1st SWR SWR SRR SRR N M I I I I I PWn M M M P1n P1n P1n P1n N Pn Pn Pn N N N N 2nd N N N N
Function Set status register Reset status register Test status register true Test status register false Test Unlock F/F Load M to PLL register Set I to UCCW1 Set I to UCCW2 Beep control Dead zone control Set timer register Set port control word Input port data to M Output contents of M to port Input port data to M Set port1 bits Reset port1 bits
Operations function (Status W-reg) N 1 (Status W-reg) N 0 if (Status R-reg) N = all if (Status R-reg) N = all if Unlock F/F (N) = all 0s, then skip PLL reg PLL data UCCW1 I UCCW2 I BEEP reg I DZC reg I Timer reg I IOS reg PWn N M (Pn) P1n M M (Pn) (Pn)N 1 (Pn)N 0
Instruction format f 1 1 1 1 0 1 0 0 0 0 0 1 1 1 0 0 0 e 1 1 1 1 0 1 0 0 0 0 0 1 1 1 0 0 0 1 1 d 1 1 1 1 0 1 0 0 0 0 0 1 1 1 1 0 0 1 1 c 1 1 1 1 0 1 0 0 0 0 0 1 0 0 1 0 0 1 1 b 1 1 1 1 0 1 0 0 0 0 0 1 1 1 1 0 0 1 1 a 1 1 1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 9 1 1 1 1 0 8 1 1 1 1 0 7 0 0 0 1 1 6 0 0 1 0 1 5 4 3 2 N N N N N r 1 0 0 1 0 I I I I I N Pn Pn Pn N N N N 1 0
0 SWR 1 SWR SRR SRR 0 1
Status register instructions
RS TST TSF TUL PLL
DH 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1
DL 0 0 1 0 1 0 1 1 1 0
Hardware control instructions
UCS UCC BEEP DZC TMS IOS IN OUT
PWn DL DL DL Pn Pn Pn Pn
DH DH DH 1 1 0 0 0 1 0 1
I/O instructions
INR SPB RPB TPT TPF
Test port1 bits, then skip if all bits if (Pn)N = all 1s, then skip 1 specified are true Test port1 bits, then skip if all bits if (Pn)N = all 0s, then skip 1 specified are false BANK I
Bank switching instructions
BANK
I
Select Bank
0
0
0
0
0
0
0
0
0
1
1
1
I
LCD instructions
LCDA LCDB LCPA LCPB HALT CKSTP NOP
M M M M I
I I I I
Output segment pattern to LCD digit direct Output segment pattern to LCD digit through LA Halt mode control Clock stop No operation
LCD (DIGIT) M LCD (DIGIT) LA M HALT reg I, then CPU clock stop Stop x'tal OSC No operation
1 1 1 1 0 0 0
1 1 1 1 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 1 0 0 0
DH DH DH DH 0 0 0 0 0 0 0 0 0
DL DL DL DL 1 1 0 0 0 0 0 1 0
DIGIT DIGIT DIGIT DIGIT I
Other instructions
No. 6472-13/14
LC72348G/W, 72349G/W
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of March, 2000. Specifications and information herein are subject to change without notice. PS No. 6472-14/14

▲Up To Search▲

Price & Availability of LC72348G

	To Download LC72348G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .